Integrated circuit memory devices are typically classified into one of two categories. These categories include random access memory (RAM) devices and read only memory (ROM) devices. Random access memory devices are typically volatile memory devices that lose their data when power to the memory is interrupted. In contrast, read only memory devices are typically non-volatile memory devices that retain their data even in the presence of power interruption. Examples of random access memory devices include dynamic RAM (DRAM) and static RAM (SRAM). Examples of non-volatile memory devices include programmable ROM (PROM), erasable programmable ROM (EPROM) and electrically erasable programmable ROM (EEPROM). A widely used EEPROM device includes flash memory, which may be classified as NAND-type or NOR-type.
FIG. 1 illustrates timing of a sequence of three operations within a memory device. Each of these operations (OPERATION 1-3) may represent a read, write or erase operation, for example. In order to perform an operation, the memory device is provided with an address and a command in sequence. This address and command may be provided by a host processor, which is electrically connected by a bus and other control lines to the memory device. Upon receipt of a command, the memory device executes corresponding operations. In the timing sequence of FIG. 1, a first address (ADD1) and a first command (CMD1) are received in sequence by the memory device. In response, the memory device executes corresponding first operations (EXE1). If the first command is a read command, the memory device may perform a read access to an internal memory array at a location defined by the first address and pass read data to an output port of the memory device. If the first command is a write command, the memory device may write new data into the internal memory array at a location defined by the first address. Finally, if the first command is an erase command, the designated first address (e.g., row address, page address, etc.) within the memory array may be erased. Once the operations associated with the first command have been fully executed, the sequence of receiving a new address and new command may be repeated. This is illustrated in FIG. 1 by the receipt of the second address (ADD2) after termination of the operations (EXE1) associated with the first command (CMD1) and the receipt of the third address (ADD3) after termination of operations associated with the second command (CMD2).